The present invention relates to current source circuits, and in particular, current source circuits utilized in Complementary Metal Oxide Semiconductor (CMOS) designs used in low-voltage applications.
There are many techniques to provide a regulated current to a load circuit. One technique involves a current mirror. A conventional current mirror provides output current proportional to an input current. Separation between the input and output current ensures the output current can drive high impedance loads. Conventional current mirror designs have been implemented in both bipolar and CMOS technology. CMOS devices with short channel lengths and therefore faster operation have provided an impetus toward current mirrors based on CMOS technology.
An important aspect in designing a CMOS current mirror is to achieve an optimum matching between the input (or xe2x80x9cbiasxe2x80x9d) current and the output current. Typically, the output current is designed to traverse a load placed across output terminals of the current mirror. A bias transistor receives the bias current and produces a proportional bias voltage. The bias voltage is then placed on an output transistor configured to replicate (or xe2x80x9cmirrorxe2x80x9d) the bias current. Properly mirrored output current assumes the bias transistor and the output transistor are fabricated with similar traits. For this reason, most modern day current mirrors are fabricated on a monolithic substrate as part of an integrated circuit.
FIG. 1 shows a conventional current mirror 5. A pair of Field Effect Transistors (FETs) N1 and N2 are shown having their gate terminals mutually connected, along with mutually connected source terminals. Since both transistors are fabricated on a monolithic substrate consistent with one another, the transistors operate in similar fashion. That is, FETs N1 and N2 can be n-type transistors or p-type transistors. Transistor N1 is connected as a diode, meaning that the gate terminal is shorted to the drain terminal.
The threshold voltage (Vt) of N1 is designed to be substantially the same as the Vt of N2. The bias current (Ibias) applied to N1 through resistor R generates a bias voltage (Vbias) at the gate terminal of N1. Vbias is substantially equal to the Vt of N1, along with additional turn-on voltage (Von) required for current flow of Ibias. The relation between Von and Ibias is described in the following equations, and is sometimes referred to as the FET square law relationship:
Ibias=K1*W/L*(Vgsxe2x88x92Vt)2,xe2x80x83xe2x80x83(1)
Where K1 is the FET gain factor, W is the channel width, L is the channel length and Vgs is the gate-to-source voltage, and where
Von=Vgsxe2x88x92Vt,xe2x80x83xe2x80x83(2)
Which reduces to
Von=(Ibias/(K1*W/L))1/2xe2x80x83xe2x80x83(3)
Von is generally referred to as the saturation voltage of the FET. If the drain-to-source voltage (Vds) of the FET is larger than the voltage Von, the FET will operate in the xe2x80x9csaturationxe2x80x9d region. On the contrary, if Vds is lower than Von, the FET will enter the xe2x80x9clinearxe2x80x9d region which, when entered, significantly degrades the gain and output impedance properties of the FET.
In the instance shown, the diode-connection of N1 forces Vds of N1 to be Vt+Von, which is larger than Von such that N1 is automatically placed in saturation. Whether N2 is in saturation or not depends on the drain voltage of node 2. The threshold voltage Vt of N1 is designed to be substantially the same as N2.
If N1 and N2 in FIG. 1 have matched parameters (channel width, channel length, threshold voltage, etc) current Ibias will be reproduced, or mirrored, through N2 as Iout. Furthermore, the mirrored current Iout will flow through whatever circuit is connected to output node 2. A circuit connected to output node 2 (interchangeably referred to as xe2x80x9cVoutxe2x80x9d) is referred to as the load of the current mirror 5.
Proper design of a current mirror must take into account at least two important characteristics involved in all current mirrors. First, the output impedance should be as high as possible. Various applications will place different impedance lower limits on the circuit. Second, the output impedance should remain as high as possible for a wide range, including the case where there is little drain to source voltage across N2, in FIG. 1. It is assumed, too, that the supply voltage is high enough to provide biasing for the current mirror circuitry.
A number of CMOS current source designs have been described previously, most of which operate to the point that the output FET device leaves the saturated region and enters the linear region of operation.
xe2x80x9cCMOS Circuit Design, Layout, and Simulationxe2x80x9d, by R. Jacob Baker, ISBN 0-7803-3416-7, IEEE (Institute of Electrical and Electronic Engineers) Order Number: PC5689, copyright 1998, provides a description of CMOS current source design techniques beginning on page 427, and describes biasing schemes that provide operation with relatively low voltage across the output stage of the current source, while maintaining the FET devices in the output stage in a saturated condition.
U.S. Pat. No. 5,966,005, xe2x80x9cLow Voltage, Self Cascode Current Mirrorxe2x80x9d by Fujimori, describes another CMOS current mirror with an output stage comprised of cascode connected FET devices.
xe2x80x9cAn Improved Tail Current Source for Low Voltage Applicationsxe2x80x9d, by Fan You, et al, in the IEEE Journal of Solid-State Circuits, Vol. 32, No. 8, August 1997, describes a high impedance current source capable of operating at low bias voltage. Although the described circuit appears to function well driving a small, fixed load, it has two loops that can potentially be unstable. Instability may result if the current source were used to drive a signal on a more heavily loaded, or more complex load, such as a computer transmission line, including discontinuities involving printed wiring board (PWB) signal wires, which have connectors, wiring vias, and so forth.
Therefore, there exists a need for a low voltage current source capable of driving PWB transmission lines with low bias voltages.
A principle object of the present invention is to provide an improved method and apparatus for providing a high output impedance current source capable of a wide range of output voltage, while driving a large capacitive load, or a load with impedance discontinuities, as are often found in Printed Wiring Board (PWB) signal carrying wires. The present invention comprises a driver and a voltage control mechanism. The voltage control mechanism is a low-gain circuit that senses the voltage on an output of the driver and adjusts the input voltage of the driver in such a manner as to maintain relatively high driver output impedance, even as the output voltage becomes close to a power supply voltage.
An embodiment of the present invention is to provide an improved method and apparatus for providing a high output impedance current source capable of reliably operating when coupled to heavily loaded or complex loads. The current source has an output voltage ranging from the entire supply voltage (Vdd) to less than a single Vds(sat), where Vds(sat) is a Field Effect Transistor (FET) drain to source voltage above which the FET is operating in its saturated region, and below which the FET is operating in its linear region.
In one embodiment, a driver""s output voltage is fed back to a voltage control mechanism. If the driver""s output voltage falls past a predetermined voltage, the voltage control mechanism adjusts an input to the driver such that the driver""s current remains substantially constant for some voltage range under the predetermined voltage.
In one embodiment of the present invention, the output voltage is compared against a reference voltage in a differential amplifier. If the output voltage is above the reference voltage, the current source operates as a conventional, non-cascode current source in which the output FET is operated in its saturated region. If the output voltage drops below the reference voltage, a gate voltage on the current source output FET will be increased in order to maintain approximately the same current, even though the FET has entered the linear region of operation. Since the output current remains relatively constant in spite of variations in the output voltage, the output impedance of the current source remains high.
In one embodiment of the present invention, a differential amplifier modifies the magnitude of a bias current entering a drain of a current mirror FET, which drain is also electrically coupled to a gate of the same FET. Modification of the bias current alters the drain voltage of the current mirror FET, which is further coupled to a gate on an output FET. The gate voltage of the output FET is modified such that the output current remains relatively constant.
In another embodiment of the present invention, a differential amplifier detects that the output voltage drops below a reference voltage and provides a current coupled to a resistor through which a bias current Ibias flows from a source of a current mirror FET, thereby raising the voltage on the source of the current mirror FET relative to a gate and drain of the current mirror FET, and reducing the bias current. The drain of the current mirror FET will rise accordingly. The drain of the current mirror FET is electrically coupled to a gate of the output FET. The rise in gate voltage of the output FET maintains a relatively constant output current, even though the output FET has entered its linear range of operation.